(1) Field of the Invention
The present invention relates to a clock generation circuit that converts an external data strobe (DQS) signal into an internal data strobe (DQSin) signal to generate an internal clock (DQSclk) signal used for hold timings of input external data (DQ1 to DQN), and also to a semiconductor memory device including therein the clock generation circuit and input circuit units (1—1 to 1—N) for the respective data signals, each of which circuit units converts an external data (DQ1 to DQN) signal into an internal data (DQ1in to DQNin) signal to latch internal data (DQ1in to DQNin) for write. In particular, the present invention relates to a semiconductor memory device capable of setting the sane setup time Ts and the same hold time Th for all waveforms of the internal data signals even in case of high-rate data signals.
(2) Description of the Related Art
FIG. 1 shows a fundamental construction of a conventional semiconductor device of this kind. As shown in FIG. 1, external input data (DQ1 to DQN) signals are input together with a reference voltage VREF to first-stage input circuits 11 of data input circuits 1—1 to 1—N, respectively.
In recent years, an increase in speed of semiconductor memory devices has been progressed. For example, DRAM (Dynamic Random Access Memory) has been developed from synchronous type SDRAM (synchronous DRAM) to DDR (Double Data Rate)-SDRAM. That is, in place of the synchronous system in which a single piece of data is exchanged at each clock pulse, a DDR system has been standardized in which each clock pulse is functionally divided to exchange two successive pieces of data at the respective rising and falling edges of the clock pulse.
Further, in a DDR2 system as a development of a DDR system, exchanges of data are successively performed at clock pulses of a clock signal CLK as shown in FIG. 2, thereby intending an increase in speed. The DDR2 system initially aimed at 300 MHz or more. However, the frequency to be coped with has increased to 667 MHz lately, as a result of progress to a very high speed.
An ordinary semiconductor memory device includes therein an input circuit unit for amplifying an external input data signal as described above to a signal of amplitude capable of operating in an internal circuit. Because the output of the input circuit unit rises and falls on the basis of rising and falling of the external input data signal, respectively, there arises a difference in rate of each of the rising and falling between the output of the input circuit unit and the external input data signal.
In general, as shown in FIG. 1, other than the external input data (DQ1 to DQN) signals input to the respective data input circuit units 1—1 to 1—N, an external data strobe signal (hereinafter referred to as DQS signal) as a high-rate signal for indicating write timings for the external input data (DQ1 to DQN) in the DDR system, is input together with the reference voltage VREF to a first-stage input circuit 2 used in common differently from the input circuit units 1—1 to 1—N.
Paying attention to the input circuit unit 1—1 by way of example, an internal data (DQ1in) signal output from the first-stage input circuit 11 is sent to two input latch circuits 12a and 12b. On the other hand, an internal data strobe signal (hereinafter referred to as DQSin signal) output from the first-stage input circuit 2 is converted into an internal clock (hereinafter DQSclk signal), which becomes latch signals (hereinafter referred to as LTSA signal and LTSB signal) different in phase by 180 degrees from each other to be sent to the respective input latch circuits 12a and 12b. 
Thus, also referring to FIGS. 4 and 5, the DQSin signal is converted into the internal clock as the DQSclk signal, which becomes the LTSA signal and LTSB signal different in phase by 180 degrees from each other to be input to the respective input latch circuits 12a and 12b. On the other hand, the internal data (DQ1in) signal amplified in and output from the first-stage input circuit 11 is latched with a difference in phase by 180 degrees in the respective input latch circuits 12a and 12b by the LTSA signal and LTSB signal different in phase by 180 degrees from each other, and then used for write into the memory at rising and falling edges of the DQS signal.
In this construction, a relative delay may occur in each rising edge and each falling edge of the DQS signal and thus the setup time Ts and the hold time Th for data write latch in the input latch circuits 12a and 12b may become uneven because of the difference in rate between the rising and falling edges. Under certain conditions, the input latch circuits 12a and 12b may latch data erroneously between high (H) level and low (L) level of the data.
To solve this problem, an input circuit, for example, as the construction of a first-stage input circuit, is disclosed in which internal input data corresponding to external input data is output differentially in accordance with currents flowing in a pair of transistors to which the external input data and a reference voltage are input, respectively, and the quantity of current of the output is controlled in accordance with the level of the internal input data (for example, see JP-A-2000-114954, FIG. 1, FIG. 4).
Further, a semiconductor integrated circuit as shown in FIG. 4 is known in which improvement of the margin between the setup time Ts and the hold time Th to be defined with respect to an input data (DQ) signal is intended to cope with an increase in speed (for example, see JP-A-2001-126481, FIG. 1, FIG. 12).
The difference of the construction of FIG. 4 from the construction of FIG. 3 is in the point that a delay circuit 13, a latch signal generation circuit 102, and a latch signal generation control circuit 103 are added.
In an input circuit unit 101, the delay circuit 13 delays the internal data (DQin) signal output from the first-stage input circuit 11 synchronously with generation of the latch signals (LTSA signal and LTSB signal) to be input to the input latch circuits 12a and 12b. Under the control of the latch signal generation control circuit 103, the latch signal generation circuit 102 generates from the output of the first-stage input circuit 2 the LTSA signal and the LTSB signal different in phase by 180 degrees from each other. The latch signal generation control circuit 103 includes therein an oscillator circuit, two sets of dummy input circuit units, and a comparator circuit. The latch signal generation control circuit 103 makes automatic control such that the difference between the delay time from a rising edge of the DSQ signal to the rising edge of the LTSA signal corresponding to the rising edge of the DSQ signal and the delay time from a falling edge of the DSQ signal to the falling edge of the LTSB signal corresponding to the falling edge of the DSQ signal is within a permissible range of zero or almost zero.
In the above-described conventional semiconductor memory device, the delay time of each of rising and falling edges of a signal to be treated is improved/controlled so that the setup time or the hold time is made even. However, at present, at which an increase in rate of signals to be treated is being progressed, particularly in case of a high-speed DDR2 system, only by the above-described technique, it is difficult to make all waveforms identical and thus a difference arises in the setup time or the hold time.
The reason is as follows. Particularly in case of the high-speed DDR2 system, because rising and falling edges of a clock are used for data write, the amplitude of a high-rate data signal externally input is very small and full swing to correspond to the high frequency to the rising and falling edges of the signal is difficult.
For example, as shown in FIG. 5, the signal waveform becomes dull due to the ON resistance of each transistor constituting the circuit, wiring resistance, and wiring capacitance, and in particular, the waveform does not reach the stable level to the power supply or ground in the second or subsequent cycle.